1. Field of the Invention
The present invention relates to a layout technology for a semiconductor integrated circuit to implement a plurality of types of semiconductor memories on a single chip.
2. Description of the Related Art
Portable equipment such as a cellular phone implements a plurality of types of semiconductor memories such as a flash memory, a dynamic RAM (hereinafter, also referred to as DRAM), and a static RAM (hereinafter, also referred to as SRAM). In response to demands for further miniaturization of the portable equipment, multi-chip packages implementing a plurality of types of semiconductor memories in a single package have been developed recently. Technologies for forming a plurality of semiconductor memories on a single chip have also been developed.
For example, Japanese Unexamined Patent Application Publications Nos. Hei 8-185695, Hei 11-86564, 2000-243078, and 2000-223589 have disclosed the technologies for forming a plurality of semiconductor memories on a single chip.
Japanese Unexamined Patent Application Publication No. Hei 8-185695 discloses the technology of sharing word lines between a DRAM core and an SRAM core and operating the DRAM core and SRAM core simultaneously.
Japanese Unexamined Patent Application Publications Nos. Hei 11-86564 and 2002-243078 disclose the technology of transferring data between a DRAM array and an SRAM array bidirectionally.
Japanese Unexamined Patent Application Publication No. 2000-223589 discloses the technology of forming different types of DRAM arrays on a single chip by equalizing the pitches of the bit line and the word line.
In the conventional art, however, no particular contrivance has been made as to the layout of the memory cells for the sake of mounting different types of semiconductor memories in combination. For example, in Japanese Unexamined Patent Application Publications Nos. Hei 8-185695 and Hei 11-86564, existing DRAM memory cells and existing SRAM memory cells are used to form the semiconductor integrated circuits. There have thus been the problems of increased development periods and development costs since the layout design (floor planning) of the memory cell arrays and the peripheries thereof requires manual procedures. In particular, the development periods increase significantly in developing a plurality of semiconductor integrated circuits having different memory capacities.
In Japanese Unexamined Patent Application Publication No. 2000-223589, a semiconductor integrated circuit is composed of 2Tr1C type memory cells and 1Tr1C type memory cells. A 2Tr1C type memory cell is formed by connecting the storage nodes of two 1Tr1C type memory cells to each other via wiring. That is, the two types of memory cells have cell transistors and capacitors of the same basic structures, so that their bit lines or word lines come to have the same pitches with no particular contrivance to the layout.